Block 1 – AM

T1: Efficient ways to lighten neural networks for circuits and systems
by Antoine Siebert, Guillaume Ferré, Bertrand Le Gal.
9:00 AM – 12:00 PM

T2: The Inverter: A Powerful Analog Building Block
by Glenn Cowan, Concordia University, Canada.
9:00 AM – 12:00 PM

Block 2 – PM

T3: Mixed Signal Approaches to Machine Learning Hardware Accelerator for Inference Engines
by Bibhudatta Sahoo, University at Buffalo, SUNY, USA.
1:00 PM – 5:00 PM

T4: High-Fidelity Sensing and Manipulation of Brain Neurochemistry
by Pedram Mohseni, Case Western Reserve University, USA.
1:00 PM – 3:00 PM

T5: Test automatization through the IEEE 1687 (JTAG) interface
by Luc Romain, Siemens, Canada.
3:30 PM – 5:00 PM

T1 : Efficient ways to lighten neural networks for circuits and systems
June 16, 2024 / 9:00 AM – 12:00 PM
by Antoine Siebert, Guillaume Ferré, Bertrand Le Gal.

— Abstract — The performance achieved by neural networks in the fields of computer vision and language processing is increasingly impressive. To obtain this, the networks contain more and more parameters, are heavy and expensive to train. In parallel with these advances, more and more data is being collected, requiring local, real-time processing, e.g. autonomous cars. Edge computing provides low latency, real-time analytics and scalability. In order to deploy these efficient algorithms on embedded devices subject to harsh constraints, neural networks must be compressed without performance degradation. This tutorial provides the main compression methods for deep neural networks, such as pruning, quantization, low-rank factorization and knowledge distillation. At the end, these methods are applied on convolutional neural network for image classification.

— Bio — Antoine Siebert received the M.S. in Telecommunications Engineering (Signal processing and AI) from ENSEIRB-MATMECA, Engineering School, Bordeaux, in 2021. He started his PhD in 2021 on embedded AI algorithms for radio communications. He worked on hybrid architectures based on Kalman filter and neural network for channel estimation. The final part of his thesis involves deploying these algorithms on embedded devices.

— Bio — Guillaume Ferré (Member, IEEE) received the Ph.D. degree in digital communications and signal processing from the University of Limoges, in 2006. From 2006 to 2008, he was a Postdoctoral Researcher with the XLIM Laboratory, Limoges, and the IMS Laboratory, Bordeaux. Since 2022, he has been a Full Professor with ENSEIRB-MATMECA, Engineering School, Bordeaux INP. After several administrative responsibilities in the Telecommunications Department, ENSEIRB-MATMECA. He is currently the Director of Industrial Relations with ENSEIRB-MATMECA. He is the author of more than 170 papers in international journals and conferences. He is also the author of 12 patents. He carries out his research activities within the IMS Laboratory in the “signal and image” team. These fields of research concern the circuits and systems for digital communications, including signal processing and digital communications, digital enhancement for wideband power amplifiers, and time-interleaved analog to digital converters. He is a member of several technical program committees. He is the Principal Investigator (PI) of many national and international projects, at the local level he is responsible for two research activities related to the IoT, including one to investigate the smart campus.

— Bio — Bertrand Le Gal received the M.S. and Ph.D. degrees from the University of South Brittany, Lorient, France, in 2002 and 2005, respectively. In 2005, he joined the IRISA/INRIA Laboratory, University of Rennes 1, and the ENSSAT Graduate Engineering School, Lannion, France, as a Teaching Assistant. Since 2006, he has been an Associate Professor with the IMS Laboratory, ENSEIRB-MATMECA Engineering School, France. In 2023, he received the accreditation to supervise doctoral research with the University of Bordeaux, France. He is the author or coauthor of 31 peer-reviewed publications in international journals and more than 100 peer-reviewed articles in international conferences. His research focused on algorithm-architecture-matching of ECC decoders on both hardware (ASIC/FPGA) and software targets (CPU/DSP/GPU). His research interests include complete digital communication system implementations and RISC-V processor design underperformance and security constraints.

T2 : The Inverter: A Powerful Analog Building Block
June 16, 2024 / 9:00 AM – 12:00 AM
by Glenn Cowan, Concordia University, Canada.

— Abstract — Analog circuits have long relied on the differential-pair as a key amplifier building block used in everything from high precision Opamps to high-speed wireline circuits. With a push to integrating analog circuits in digital-optimized technologies, the early 2000s saw a resurgence of interest in inverter-based circuits, particularly in wireline applications. Examples include source-series terminated line drivers, inverter-based transimpedance amplifiers, optical receiver main amplifiers as well as continuous-time linear equalizers. This talk presents an overview of early work in inverter-based amplifiers from the 1960s and 70s that was revived in the late 80s/early 90s for continuous-time filters. A variety of work, mainly for wireline applications will be surveyed, demonstrating the breadth of analog circuit application of the humble CMOS inverter.

— Bio — Glenn E. R. Cowan received the B.A.Sc. degree from the University of Waterloo, Waterloo, ON, Canada in 1999, and the M.S. and Ph.D. degrees from Columbia University, New York, NY, in 2001 and 2005, respec;vely. In 2005, he joined the Communica;ons Technology Department at the IBM T. J. Watson Research Center, Yorktown Heights, NY. In 2007, he joined the Department of Electrical and Computer Engineering at Concordia University in Montreal, QC, Canada, where he is a Professor. At Columbia, Dr. Cowan was a 2003 recipient of Analog Device’s Outstanding Student Designer Award. He was the 2005 recipient of Columbia’s Eliahu I. Jury award for outstanding achievement by a graduate student in the areas of systems, communications, or signal processing. His current research actvities include low-power mixed-signal circuits for biomedical applica;ons and wireline communica;on, as well as mixed-signal computa;on.

T3 : Mixed Signal Approaches to Machine Learning Hardware Accelerator for Inference Engines
June 16, 2024 / 1:00 PM – 5:00 PM
by Bibhudatta Sahoo, University at Buffalo, SUNY, U.S.A.

— Abstract — The rapid advancements in computing, communication, and networking technologies facilitated by the feature size scaling of transistors, have not only made connected devices, i.e., Internet-of-Things (IoT), possible but also resulted in volumes of data being generated by these devices, which has led to rapid advancements in the area of big-data analytics thereby ushering in a new era of artificial intelligence and machine learning hardware to make smart connected devices. We have reached an inflection point in the design of such smart connected devices: the machine learning hardware designer must look beyond conventional digital computing blocks and possibly revive analog computing. This has led to a new generation of analog designers who are combining conventional analog circuits with approximate computing techniques to build energy-efficient systems. This tutorial begins with an overview of various Neural Network Architectures and the computing blocks needed to realize them. FPGA-based Convolutional Neural Network (CNN) architectures for energy-efficient inference engines for image/depth-image classification, and seizure prediction which also reduces the sensor-interface front-end power and the energy-per-bit needed to transmit the sensor information to the inference engine will be discussed next. Hardware techniques for memory augmented neural network (MANN) will be discussed as well. Various analog dot-product computation methodologies, viz., conductance-based, charge-based, and gm-based will be discussed next. An oscillator-based mixed-signal Spiking Neural Network (SNN) architecture and techniques to facilitate energy-efficient training-on-the-edge will be presented.

— Bio — Bibhu Datta Sahoo is currently a professor in the Department of Electrical Engineering at University at Buffalo, State University of New York (SUNY). He received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kharagpur, India, in 1998, the M.S.E.E. degree from the University of Minnesota, Minneapolis, MN, USA, in 2000, and the Ph.D.E.E. Degree from the University of California, Los Angeles in 2009. From 2000 to 2006, he was with DSP Microelectronics Group, Broadcom Corporation, Irvine, CA, where he designed analog and digital integrated circuits for signal-processing applications. From December 2008 to February 2010, he was with Maxlinear Inc., Carlsbad, CA, where he was involved in designing integrated circuits for CMOS TV tuners. He has been a faculty at IIT Kharagpur, India and Amrita University, India. His research interests include mixed signal circuit design, analog computing, and machine learning hardware. He received the 2008 Analog Devices Outstanding Student Designer Award and was the co-recipient of the 2013 CICC Best Paper Award. He was the Associate Editor of IEEE Transactions on Circuits and Systems-II from Aug. 2014 to Dec. 2015. Since Aug. 2019 he has been the Associate Editor of IEEE Open Journal of Circuits and Systems.

T4 : High-Fidelity Sensing and Manipulation of Brain Neurochemistry
June 16, 2024 / 1:00 PM – 3:00 PM
by Pedram Mohseni, Case Western Reserve University, USA.

— Abstract — New enabling technologies for real-time, high-fidelity sensing and manipulation of brain neurochemistry at microscopic scales can provide the framework for ultimately developing new neuromodulation devices that impose therapeutic neurochemical profiles or maintain optimal neurochemical levels in disease states via real-time feedback control. This tutorial will first cover the fundamentals of fast-scan cyclic voltammetry (FSCV) at a carbon-fiber microelectrode (CFM) as the preferred method for probing brain neurochemical dynamics with high temporal, spatial, and chemical resolution. The tutorial will next focus on CMOS-integrated systems that combine FSCV-based recording, embedded signal processing, and electrical stimulation on a single chip for high-fidelity manipulation of brain neurochemistry. System-level solutions to handle stimulus artifacts along with chemometrics algorithms to resolve the target analyte from common interferents in vivo will be discussed. Two such systems realizing a dopamine temporal pattern generator and a dopamine “neurochemostat” will be showcased and validated in vivo in a rodent model. The tutorial will conclude with a discussion of new directions in neurochemical monitoring such as compressive sensing (CS) for real-time neurochemical data compression and high-fidelity reconstruction as well as circuit techniques for in situ analog background current subtraction. These directions are envisioned to pave the way toward high-channel-count sensing of brain neurochemistry.

— Bio — Pedram Mohseni is the Goodrich Professor of Engineering Innovation and Inaugural Chair of the Electrical, Computer, and Systems Engineering Department at Case Western Reserve University, Cleveland, OH, USA. He received the B.S. degree from the Sharif University of Technology, Tehran, Iran, in 1996, and the M.S. and Ph.D. degrees from the University of Michigan, Ann Arbor, MI, USA, in 1999 and 2005, respectively, all in electrical engineering. His main research interests are in analog/mixed-signal/RF integrated bioelectronics, wireless power/data tranfer to biomedical implants, translational microfluidics, and microassays for point-of-care/point-of-injury diagnostics. His research activities have resulted in 2 book chapters, over 150 refereed publications, and 14 issued U.S. and international patents. He was the General Chair of the 2018 IEEE Biomedical Circuits and Systems (BioCAS) Conference and currently serves as the Editor-in-Chief of the IEEE Transactions on Biomedical Circuits and Systems (TBioCAS). Dr. Mohseni was inducted into the U.S. National Academy of Inventors (NAI) in 2023 as a Senior Member for producing biomedical technologies that have brought, or aspire to bring, real impact on the welfare of society.

T5 : Test automatization through the IEEE 1687 (JTAG) interface
June 16, 2024 / 3:330 PM – 5:00 PM

— Abstract — The IEEE 1149.1 JTAG standard is used in practically all designs today, as it provides methods and tools to interact with the IP inside the chip.  However, the increasing complexity of today’s designs introduces scalability challenges such as integration of the 1149.1 JTAG IP and patterns retargeting. The IEEE 1687 IJTAG standard solves this challenge by using a scalable approach during design, pattern generating, and retargeting. The objective of the presentation is to provide a detailed overview of the IEEE 1687 IJTAG and how it extends the 1149.1 JTAG standards. Examples demonstrate how test instruments and custom IP can easily be integrated in the IJTAG network.  Finally, we introduce the Siemens Tessent platform and how it can be used to automatically create the IJTAG network, create verification testbenches, and generate manufacturing patterns. The content of this presentation is aimed for IP developers, design architects, and project managers.

— Bio — Luc Romain is a Principal Software Development Engineer at Siemens where he develops design-for-test tools. He has been working in the EDA industry since 1999. He is based in Ottawa, Canada. His main area of expertise is IC memory test, redundancy analysis and self-repair. Luc holds a bachelor and a master’s degree in Electrical Engineering from Ecole Polytechnique de Montreal.