Reality Labs : Augmented Reality silicon challenges at and research directions
by Édith Beigné, Director of Silicon research, Meta (formerly The Facebook company) Reality Labs

How we got here.  Where we’re headed.
by John East

The Future of Short Reach Interconnect: A SerDes Perspective
by Davide Tonietto, Huawei Canada

Reality Labs : Augmented Reality silicon challenges at and research directions
Édith Beigné
Director of Silicon research, Meta (formerly The Facebook company) Reality Labs

— Abstract — Augmented reality (AR) is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware and accessible user interface delivered through a socially acceptable form factor such as eyeglasses. One of the biggest challenges in realizing a comprehensive AR experience are the performance and form factor requiring new custom silicon. Innovations are mandatory to manage power consumption constraints and ensure both adequate battery life and a physically comfortable thermal envelope. This presentation reviews Augmented Reality applications at Facebook Reality Labs and Silicon challenges.

— Biography — Edith Beigné is the Research Director of AR/VR Silicon at Meta Reality Labs where she leads research projects driving the future of AR devices. Her main research interests are low power digital and mixed-signal circuits and design with emerging technologies. Over the past 20 years, she has been focusing her research on low power and adaptive circuit techniques, exploiting new design techniques and advanced technology nodes for different applications ranging from high performance multi-processors to ultra-low power SoC, and, more recently, AR/VR applications. She is the chair of ISSCC 2022 and part of ISSCC TPC since 2014, she was part of VLSI symposium TPC between 2015 and 2020. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. She visited Stanford University in 2018 to research on emerging technologies and new architectures.

How we got here.  Where we’re headed.
John East

— Abstract — Roughly 120 years ago the field of electronics began with the invention of the vacuum tube.  The next 50 or 60 years were mostly dedicated to RF,  to improvements in radio, television, and radar technology.  Digital electronics were mostly relegated to the role of laboratory curiosities. The invention of the transistor in 1947 didn’t change that situation as much as one might expect because of what was referred to as the “wire problem”.  The invention of the integrated circuit in 1959 unleashed what is commonly referred to as the digital revolution.  The fires of the digital revolution were stoked by Moore’s law. To keep the revolution going at full speed, higher and higher levels of integration were necessary and Moore’s law guaranteed that those would be available.  Today there is some question of how much longer Moore’s law will hold.  There is also a question of how much it will matter? Will the progress over the next few decades depend on integration level as much as the last few did?  And if not, what will be the keys to success over the coming decades?

— Biography — John East retired from Actel Corporation in November 2010 in conjunction with the transaction in which Actel was purchased by Microsemi Corporation.  He had served as the CEO of Actel for 22 years at the time of his retirement.  Previously, he was a senior vice president of AMD, where he was responsible for the Logic Products Group.  Prior to that, Mr. East held various engineering, marketing, and management positions at Raytheon Semiconductor and Fairchild Semiconductor.  In the past he has served many boards of directors and advisory boards for companies serving various aspects of the high-tech market.  He currently serves on the boards of directors of SPARK Microsystems – a Canadian start-up involved in high speed, low power radios — and Tortuga Logic — a Silicon Valley start-up involved in hardware security.   He is presently an advisor to Silicon Catalyst — a Silicon Valley based incubator actively engaged in fostering semiconductor-based start-ups.  His education and work histories are chronicled by the Computer History Museum, as well as in the Stanford University Library / Silicon Genesis. Mr. East holds a BS degree in Electrical Engineering and an MBA both from the University of California, Berkeley.  He has lived in Saratoga, California with his wife Pam for 49 years.

The Future of Short Reach Interconnect: A SerDes Perspective
Davide Tonbietto
Huawei Canada

— Abstract — The unprecedented information explosion and its exponentially increasing demands on data traffic and processing are pushing a rapid and diverse evolution in short reach interconnect technologies. In the background of this race, CMOS technology is not providing the usual node over node boost in performance to help SerDes designers cope with higher bandwidth and data rates. Breakthroughs in high speed electrical interconnect and new approaches in optical interconnect, such SiPho, NPO (near package optics) and CPO (co-packaged optics) promise improved performance, energy efficiency and density. How are these new technologies going to affect the ever more complex power and density problems facing SerDes design? What are the specific challenges that new and emerging applications such as AI and HPC are posing on SerDes architectures and design? How interconnect technologies and new SerDes architectures are going to respond to the need for die disaggregation and multi-die IC products?

— Biography — Davide Tonietto graduated in Electrical Engineering from Pavia University, Italy in 1996. He has worked in several IC companies as analog IC designer and technical manager. He holds more than 20 US patents in the areas of Analog and Mixed Signal IC design and wireline communication systems and authored several papers on the subjects. He joined Huawei Canada in 2011 where he is currently Huawei Fellow and Senior Director. He founded and leads Hisilicon Serial Link (HiLink) a global organization based in Canada and China which supplies Hisilicon with a complete SerDes IP platform targeting all Huawei products and applications: Networking, Datacenter, HPC, Wireless Infrastructure, Mobile & Consumer. His research interests are in the areas of SerDes architecture, design, optimization and testing. He is currently involved in the definition of the technology roadmap for Near Package and Co- Packaged Optics (CPO and NPO).